Time delay in a mechatronic Power-HIL system: Analysis and model-based compensation

Abstract

The Power-Hardware-in-the-Loop (PHIL) methodology enables testbed solutions that support the development of complex mechatronic components. In PHIL testing, a unit under test (UUT) is coupled with a virtual representation of its surroundings. As an example, a real railway pantograph current collector UUT can be tested in real-time interaction with a virtual overhead catenary. However, due to the closed-loop feedback interconnection and the exchange of power between real and virtual systems, such a PHIL control structure is highly sensitive to time delays in the signal paths which limits its performance, accuracy, and stability. In this work, methods to evaluate and compensate for the effect of time delays in a typical PHIL structure are proposed. A model-based PHIL control system is introduced to demonstrate the effect of time-delay compensation techniques, including utilising specific reduced-order models to achieve efficient time-delay compensation. The performance of the control system is demonstrated and validated via simulations and experiments on a scaled PHIL test setup, which is related to railway pantograph testing. In addition, criteria to analyse system stability are formulated and demonstrated with respect to uncompensated time delays and unknown UUT contact stiffness.