Network on Chip is a communication system used in integrated circuits as an alternative to bus systems. Instead of all chip elements exchanging their data directly or via a bus, packets containing the information are sent over different topologies between source and destination, which can be for example a storage element or a processing unit. Fault tolerance of such systems is of critical importance due to its role as communication backbone. Additionally, the increasing number of elements on a chip and its complexity introduce more possibilities for faults in the circuits. A common way to improve the fault tolerance is to implement additional mechanisms like error correction code, adaptive routing algorithms, or re-transmission of packets. However, how do these measures perform if they themselves become faulty? Furthermore, how does this affect the performance of the Network on Chip? Here it is shown that the impact of faults on fault tolerance in Network on Chips needs to be evaluated during the design process. The network was evaluated by adding fault modules into the source code and triggering them to represent certain fault patterns. The results show that the fault tolerance measurements affect the reliability differently for certain faults and partly let the network perform worse than without any tolerance measurements activated. This emphasizes the importance of this evaluation and that it should be considered and applied for designing such systems. This work is seen as a starting point to investigate if the fault injection process can be used to improve the sturdiness of such systems. Furthermore, it is seen as a convenient way, also for other research groups, to evaluate the behavior of a system under the effects of faults. The fault injection methods are not bound to this project and can be used for other Verilog Code based systems as well.