Billions of High Frequency (HF) Radio Frequency IDentification (RFID) cards/tags are manufactured with a significant increase each year in the market of RFID applications. This drives the industry to investigate different aspects in order to reduce the manufacturing costs and enhance the cards lifetime. One of the methods to achieve these goals is to remove the electrically conducting (“galvanic”) connection between the cards body and the Integrated Circuit (IC) since the galvanic connection is costly in manufacturing and reduces the cards robustness against mechanical stress. We investigate different designs for HF RFID cards with non-galvanic connection between the cards body and the IC starting from the fundamental Bode-Fano limit. This investigation leads us to introduce the non-galvanic booster-based cards designed to achieve the same power transfer levels as the conventional galvanic cards. Our booster-based cards are also more flexible in achievable bandwidth designs for a given IC. However, this flexibility comes at the expense of higher design complexity. We also investigate a rather recent non-galvanic card design that uses a metallic Coupling Frame (CF) with a slot and a gap, instead of the conventional coil structure. This type of cards existed for several years without any explanation of its principle of operation. We explained its operation by basic electromagnetic principles and Finite Element Method (FEM) simulations, where we proved that it operates through inductive coupling, rather than capacitive coupling as this was assumed previously. Further, we introduced two enhanced designs for such metallic CFs. Though the non-galvanic cards solve some real-world challenges for HF RFID cards, their design still needs to be optimized to pass several standardized tests before commercial use. Through our investigations, we found that the IC frontend significantly limits the cards operation range. We investigate the specified IC model components that are defined by the standard within the Reference Proximity Integrated Circuit Card (PICC), where we analyze its basic three circuits and also introduce a simplification and an enhancement to its design. We also introduce a novel method to model commercial ICs leading to higher modeling accuracy compared to existing methods. Further, we measure and calculate the first model of the HF RFID IC when it is communicating by load modulation. Moreover, we investigate the ICs requirements to communicate at all the basic bit rates specified in the standard. These investigations shed a light on many restrictions that need to be accounted for in the cards optimization criterion to pass the standardized tests. Finally, we formulate a constrained minimization problem that accounts for all these aspects to render a standard-compliant galvanic card and we extend this approach also to non-galvanic cards. The results of this optimization algorithm are verified by prototypes on booster-based cards that pass the standardized tests for all basic bit rates.