State-of-the-art bulk silicon RF antenna switches are built by multi-nger nMOSFET transistors connected in stacked conguration, i.e. the transistor blocks are connected in series. Due to the critical location in the RF antenna front-end, an electrostatic-discharge (ESD) self-protection approach is the normal choice to not degrade the RF performance. This fact implies that the stacked devices must be studied in a broad bias operations to detect possible causes of weaknesses, high leakage and low ESD robustness. In this thesis work, the ESD behavior of stacked multi-nger transistors for RF an-tenna switch applications for 0.13 m bulk silicon technology is analyzed by means of a combinations of experiments and simulations. Several measurements technique are exploited for the investigation, like transmission line pulse (TLP) technique, transient interferometric mapping (TIM) technique and emission microscopy (EMMI) technique. Moreover, due to the complexity of the stacked devices, SPICE simulations are used to have deeper understanding of the transient evolution of all transistors belonging to the stacked conguration of CMOS blocks. The reasons of weak product device performances are investigated on both single transistor device and stacked transistor test structures. Dedicated measurements are presented for creation of accurate models able to cover a wide operation range under ESD conditions and for calibration of TIM measurements. Thanks to all of this, we explain unique TLP waveforms and power dissipation on stacked devices discovering the impact of the interaction of the CMOS blocks via substrate.