This master's thesis deals with the interface trap characterization of Si-face 4H-SiC (siliconcarbide) metal-oxide-semiconductor (MOS) structures realized by dry thermal oxidation. First, a detailed theoretical study of the 4H-SiC MOS structure in a wide temperature range is done to obtain theoretical Capacitance-Voltage (CV) curves. Experimentally, the Dit distribution is extracted using the high frequency Terman method, the low frequency capacitance method, the high-low frequency method and the conductance method in a temperature range from 150 to 600 K. Within this thesis a custom-built quasi-static (QS)-CV measurement circuit based on the improved feedback charge method is designed and realized and shows a high accuracy and a very low offset current. For a more detailed characterization mobile charge densities using the bias temperature stress (BTS) and the triangular voltage sweep (TVS) method are determined as well as breakdown measurements are performed. A very good agreement between the different interface trap characterization methods and rather low Dit values are extracted in a wide energy range of 0.05 eV up to 0.85 eV below the conduction band. Three different types of interface traps are identified. Besides the classic interface traps both near interface oxide traps (NIOTs) with a large response time constant and traps with a very short time constant are found additionally. The mobile charge density is measured to be in the 2x10^12 cm^2 range. A large influence of pre-oxidation substrate cleaning to all investigated parameters is demonstrated.