The rapidly increasing interest in high speed access networks and large capacity communication encouraged the advancement of low-cost optical transmission systems. The tendency to design highly integrable and low cost broadband optical systems, makes it desirable to realize optoelectronic circuits such as transimpedance amplifiers (TIAs) and laser diode drivers (LDDs) in CMOS technology. Since advanced CMOS technology introduces challenges regarding the design of such circuits, the need of lower power dissipation and higher integrability motivates further research on new circuit topologies. This dissertation shows that nanometer CMOS technology can be used to design two of the most vital blocks in a typical optical transmission system, namely, the TIA in the optical receiver and LDD in the optical transmitter. Main focus of this thesis is to propose new topologies to overcome the technology limitations and allow the implementation of low power compact TIAs and a high voltage LDD. The circuits are all designed in standard 40nm CMOS technology. On the receiver side, three novel different inductorless TIAs are presented. For measurement purposes, the TIAs are integrated with a chain of voltage amplifiers and a 50 - output buffer. The first TIA is implemented using a push pull current mirror (PPCM) with a feedback resistor. Experimental results show that this TIA achieves a power efficiency of 0.324 mW/Gb/s from a 1.2V supply at a maximum data rate of 10Gb/s. The whole design occupies an active area of 51x96 µm2. The second TIA is implemented using a common drain active feedback (CDAF). Measurement results show that this TIA acquires a power efficiency of 0.3 mW/Gb/s from a 1.2V supply at a maximum data rate of 8Gb/s. The full design occupies an active area of 33x101 µm2. The third TIA introduces a regulated cascode TIA with an active feedback (RGCAF). Experimental results show that the TIA achieves a power e_ciency of 0.24mW/Gb/s m from a 1.2V supply at a maximum data rate of 10Gb/s. The whole design occupies an active area of 44x89 µm2. In comparison with the state-of-the-art the proposed TIAs show a competitive power efficiency while occupying minimum chip area. On the transmitter side, a high voltage LDD is implemented. An open drain double cascode fully differential structure is used to provide a high modulation current of up to 80mA and to guarantee a reliable operation of the devices under high voltage condition. To reduce power consumption, the LDD is supplied by 1.1V for the pre-driver and 5V for the output stage. Measurement results show a step response with rise and fall times (10%- 90%) of 209ps and 153ps, respectively. Therefore the LDD can operate at a data rate of 3Gb/s.