Technology scaling has made the transistors increasingly susceptible to radiation particle strikes. As a consequence, particles with lower energy which are substantially more frequent can already cause non-destructive single event effects in CMOS circuits. Understanding them is not very straightforward, as there are so many parameters involved along with these effects, like radiation particle strikes strength, target circuit, path of propagation, and surrounding environment. Our goal in this thesis is to study these effects in digital CMOS circuits and aid construction of efficient radiation tolerant circuits. Firstly, the effectiveness of the existing radiation hardening techniques to particle hits in digital CMOS circuits has been mainly studied in this thesis (under a given set of environmental conditions). ^We explicitly analyze how the performance of two selected radiation hardening techniques, namely transistor sizing and stack separation, when exposed to particle hits varies with temperature and supply voltage. We present design aims and concepts as well as implementation results of a digital ASIC that is dedicated as a target for long-term irradiation experiments. Its sole purpose is to study susceptibility to radiation as well as propagation of radiation effects, and aid in understanding the same. The infrastructure should be able to record the SETs, in spite of the need of being tolerant to particle strikes in itself that cannot be avoided in some types of radiation experiments. The problem of devising a suitable infrastructure lies in the partly contradictory requirements, like constrained area, radiation tolerance and good resolution of the location and propagation path of particle hits. This was a major challenge in our thesis. ^To analyze single-event-transient (SET) sensitivity in digital CMOS circuits we propose an on-chip measurement architecture for various target circuit blocks. We also propose an architecture that allows tracing, generation and propagation of SETs in the Sklansky adder and inverter tree. Our measurement architectures are based on non-rad-hard counters namely, linear feedback shift registers and Muller pipeline based up/down counters. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET).We show that the infrastructure is resilient against double faults, as well as many triple and even higher-multiplicity faults. ^Together with a probabilistic analysis and fault dictionary we can conclude that the proposed architectures will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure. Finally to measure SET pulsewidths in any digital circuit a unique on-chip measurement infrastructure is proposed. Unlike the known oscilloscope-based methods, our approach is all-digital: SET durations are measured by the SET-gated counting of pulses generated by a high-frequency ring oscillator, and stored in an up/downcounter array organized in a ring. We carefully elaborate a comprehensive concept for making our infrastructure SEU tolerant, again with the main challenge being to attain a sufficiently high probability of recording useful hits in the target before exhausting the SEU tolerance of the infrastructure. ^Our key contribution here concerns the protection of the counter array: Rather than resorting to radiation hardening or explicit triple modular redundancy (TMR), we save area by using a novel redundant duplex counter architecture: For a small number of recorded SETs, our architecture implicitly implements TMR, albeit in a way that degrades gracefully for larger numbers of recorded SETs. We have presented the measurement infrastructure and a detailed pre-fabrication analysis of the circuits hosted in the digital ASIC. We sketch our respective solutions for the on-chip transmission architecture and present the resulting area distribution of the final ASIC layout which has been performed for an industrial 65nm bulk CMOS process. We also show how we optimized the layout for the purpose of our experiments and present all relevant implementation details. The datasheet of the ASIC that is of paramount importance is presented in great detail. ^Moreover, an overview of the experimental setup is presented and some specific details are highlighted.