A directions of arrival (DOA) estimator based on sparse Bayesian learning (SBL) is implemented as a xed-point prototype for an FPGA platform. The prototype is developed mainly using high-level synthesis (HLS) of C++ based model specifications. Prototyping possibilities are explored for incremental veri cation with well known computing environments. For modeling, the equations of the algorithm are reduced to arithmetic operations considering the signal ow within the iterative structure. The relevant as- pects of the used HLS tool, Vivado HLS, concerning fixed-point data types, methods for creating hierarchical designs, and specific modeling techniques are discussed. The prototype is presented in detail. Scheduling of each module is done as soon as possible to make use of the parallel FPGA architecture. Different xed-point word length assumptions are explained and implementation results are shown in terms of resources, latency, and power consumption estimates. Finally, a representative DOA source example is simulated and tested with the imple- mented prototype hardware in the loop. The comparison with a floating-point reference implementation is found to have good agreement with the fixed-point implementation.