Titelaufnahme

Titel
Characterization and modeling of charged defects in silicon and 2D field-effect transistors / von Yury Illarionov
VerfasserIllarionov, Yury
Begutachter / BegutachterinGrasser, Klaus-Tibor ; Waltl, Michael
ErschienenWien, 2016
Umfangvi, 121 Blätter : Diagramme
HochschulschriftTechnische Universität Wien, Dissertation, 2016
Anmerkung
Zusammenfassung in deutscher Sprache
Titelübersetzung des Autors: Charakterisierung und Modellierung von Defekten in Silizium und 2D Feldeffekttransistoren
SpracheEnglisch
Bibl. ReferenzOeBB
DokumenttypDissertation
Schlagwörter (DE)Zuverlässigkeit / Defekte / MOS Transistoren / 2D Materialien / Graphene / MoS2
Schlagwörter (EN)Reliability / Defects / MOS Transistors / 2D Materials / Graphene / MoS2
URNurn:nbn:at:at-ubtuw:1-82621 Persistent Identifier (URN)
Zugriffsbeschränkung
 Das Werk ist frei verfügbar
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Characterization and modeling of charged defects in silicon and 2D field-effect transistors [15.71 mb]
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Zusammenfassung (Englisch)

This work has been conducted at a time when scaling of Si MOSFETs according to Moore's Law is close to its end. Hence, the research focus is shifting from nanoscale Si MOSFETs to nextgeneration transistors based on 2D materials. Although these technologies are dramatically different from one another, the question of reliability is essential for both types of devices. However, the typical dimensions of modern nanoscale SiMOSFETs are already far below 100 nm, while the channel lengths of next-generation 2D FETs are still in micrometer range. Hence, in the former case the reliability is dominated by single discrete defects and in the latter case one has to deal with the impact of continuously distributed defects. In the course of this dissertation we characterize the reliability of both nanoscale Si MOSFETs and next-generation 2D FETs with graphene and molybdenum disulphide (MoS2) channels. First we study the impact of charged traps and random dopants on the performance of nanoscale Si MOSFETs. Based on the results of TCAD simulations, we introduce a precise technique which allows for evaluation of the lateral trap position from the experimental data obtained using time-dependent defect spectroscopy. While our method fully accounts for the impact of random dopants, the typical uncertainty is several percents of the channel length. Next we switch our attention to graphene FETs and analyze their reliability with respect to bias-temperature instabilities (BTI) and hot carrier degradation (HCD). Our analysis shows that the degradation/recovery dynamics of BTI and some HCD mechanisms can be captured using the models previously developed for Si technologies. Also, we show that HCD in graphene FETs can either accelerate or suppress BTI degradation, depending on the bias condition. In some cases this leads to a non-trivial impact on charged trap density and carrier mobility, both of which are correlated to each other. Finally, we study the reliability of MoS2 FETs, which are more suitable for applications in digital circuits compared to graphene transistors. While analyzing the hysteresis and BTI in these devices, we demonstrate that our MoS2 FETs are more stable compared to their previously reported counterparts. Moreover, we show that use of hexagonal boron nitride as a gate insulator significantly improves the reliability of MoS2 FETs, especially at low temperatures. Lastly, we introduce the proof of concept for modeling of the reliability characteristics of MoS2 FETs using advanced simulation software previously developed for Si MOSFETs. The results obtained for 2D FETs allow for a general understanding of their reliability at the beginning stage of research. However, sooner or later circuit integration of these new devices will request considerable scaling of their dimensions and dramatical improvement of the technology level. As so, reliability of 2D FETs will be also dominated by single defects. Thus, we can expect that our trap location technique developed for nanoscale Si MOSFETs, as well as the described modeling approach, can be applied for next-generation 2D FETs in future.