Within the past 20 years the speed of processors has grown much faster than that of memories. To bridge the resulting performance gap, caching has been introduced. This thesis describes the completely redesigned memory layer for the SPEAR2 core which serves as basis for the integration of an appropriate cache controller. SPEAR2 (Scalable Processor for Embedded Applications in Real-time Enviroments) is a RISC microprocessor architecture that was developed at the Department of Computer Engineering at the Vienna University of Technology. Thanks to its real time capability and its modular structure, this processor is especially suited to be used in embedded systems. In order to expand the application area of the processor and to use the full address space provided by the architecture, the SPEAR2 core must be equipped with additional storage capacity, i.e., data and instruction memory need to be displaced into an external RAM module. The beneﬁt of this approach comes at the cost of a performance degradation as the SPEAR2 pipeline suffers from additional wait states caused by the increased latency resulting from external memory accesses. The implementation of an adequate cache controller therefore seems to be obligatory. After providing a detailed theoretical background concerning the fundamental aspects of caching together with more sophisticated techniques, this master thesis proceeds with simulations in order to ﬁnd an appropriate caching strategy under given constraints. The reader will be introduced to SPEAR2SIM, a novel simulation environment for the SPEAR2 instruction set architecture that allows an efﬁcient performance assessment of different caching strategies from which three candidates are selected. Their simulation results will be compared against the results of an experi- mental study in VHDL in order to be able to select the best adapted caching policy for a given application. Furthermore, practical problems and challenges of designing an efﬁcient cache controller for the given architecture will be pointed out. As a result of this thesis, a novel prototype of the SPEAR2 processor with a new memory layer that can be equipped with three different cache controllers (direct mapped, fully associative and two-way set associative) is available.