Temporal and spatial partitioning ensure that one component cannot interfere with the correct behavior of other components in the value and time domain. The time-triggered system-on-chip (TTSoC) architecture provides a framework for the design and implementation of systems-on-chip (SoCs) with inherent temporal and spatial partitioning.
Multiple heterogeneous IP-cores are interconnected by a time-triggered network-on-chip (TTNoC), which uses a precise interface specification to encapsulate the communication activities of components. To dynamically adjust the system to changing communication and power requirements, integrated resource management is provided. Within this thesis, the effectiveness of temporal and spatial partitioning in the TTSoC architecture is investigated. Therefore, an experimental FPGA-based setup is designed using the TTSoC execution platform. This setup allows the injection of faults in the system, while monitoring the behavior of components. The system is exposed to different load scenarios, bit flips that simulate transient and permanent faults, and reconfiguration scenarios, to observe the system behavior in the presence of faults. The results of the experiments provide evidence for the correctness of temporal and spatial partitioning and demonstrate the suitability of the TTSoC architecture as an execution platform for component-based design.