Synchronous chip designs have been in use for plenty of years and performed well. Fully developed software solutions and custom hardware targets spare the programmer most questions concerning synthesis and Place&Route. The underlying algorithms try to find an optimal solution. Increasing demands on speed and power consumption lead the synchronous chip design to its physical limitations. Signal propagation delay and heat development hinder further clock advancement. Clock distribution is a major problem.
Asynchronous chip design solves most of the problems in a natural manner and offers an elegant design alternative with increasing research interest.
No clock net is necessary and speed adopts to the circuit's conditions, controlled by a handshake protocol. This thesis covers the asynchronous control-, and data flow by means of the concrete implementation of a special UART in four state logic (FSL). The UART exploits a feedback loop to generate an oscillation (jitter-afflicted). The oscillation is used to derive a timebase. The performance of the UART is examined in terms of keeping a specific baud rate.
An essential part of this thesis is dedicated to simulation. A simulation model has been created to support FSL circuit development. By means of this model, control and data flow as well as possible deadlocks can be analysed at a high abstraction level. Moreover, discrete event simulation is covered and its function explained on the basis of an HDL simulator. Simulation at different abstraction levels of the above-mentioned UART completes the simulation part.