The importance of System-on-Chip and System-in-Package solutions in the domain of embedded systems was steadily increasing during the last years. Due to the rising complexity of embedded applications and irregular processor architectures, highly optimizing compilers are needed to meet the stringent chip area and power dissipation requirements of such platforms.
The energy consumption of current processors is dominated by the dynamic power dissipation, which can be reduced largely by minimizing the number of memory accesses, minimizing execution cycles, and minimizing switching activities on buses.
This thesis contributes improvements on register allocation for an irregular architecture which reduce memory accesses and execution cycles, and a post-pass code optimization for minimizing the dynamic switching on the instruction memory bus. The techniques presented in this thesis are implemented in the context of the xDSPcore architecture which will be introduced shortly.