The Time-Triggered System-on-a-Chip (TTSoC) architecture provides an integrated execution environment for the component-based development of many different types of embedded applications (e.g., automotive, avionics, consumer electronics). At the core of this architecture is a time-triggered Network-on-a- Chip (NoC) for the predictable interconnection of IP cores.
This thesis contributes to the TTSoC architecture by designing a Uniform Network Interface (UNI) that supports the integration of multiple heterogeneous IP cores-belonging to different criticality-classes and application domains-into a single SoC. The UNI is implemented by a dedicated hardware component called the Trusted Interface Subsystem (TISS), which is replicated for each IP core. The TISS controls the IP core's access to the time-triggered NoC and provides encapsulation mechanisms that prevent any unintended interference between IP cores, which is a major requirement for the integration of mixed-criticality subsystems.
Exploiting the inherent fault isolation and determinism of the architecture, we introduce a novel concept for fault-tolerance based on the replication of entire IP cores organized in Triple Modular Redundancy (TMR) configurations.
With respect to TMR we have investigated two different approaches. While on-chip TMR realizes the replicas in the same SoC to increase the reliability of services residing on a single chip, off-chip TMR instantiates the replicas on different SoCs interconnected by a fault-tolerant off-chip network, as it is required for ultra-dependable systems.
Complementing the architectural framework, we have introduced a novel naming scheme tailored to the unique challenges of large embedded systems based on multi-processor SoCs. The naming scheme supports independent development of application subsystems by providing a dedicated, independent, and domain-specific namespace for each application subsystem and facilitates dynamic resource management by decoupling the logical and the physical system structure.