Code Alternation Logic is based on the utilization of two representations of "high" and "low" in two different phases phi0 and phi1. The representations are used alternatively, so within a sequence of data words each bit can uniquely be assigned to the corresponding data word. In contrast to the conventional synchronous design flow, our CAL design flow comprises two synthesis steps. A main goal of this thesis is to analyze the delay insensitivity of a circuit implementation with CAL. For this purpose pipeline stages as well as basic gates are transformed to timed automata and analyzed with the model-checker Uppaal. In this thesis the delay insensitive behavior of pipeline structures and the correctness of the combinational logic between these stages is proven. Up to this point hardware independent models of the basic gates are used for constructing these combinational logic functions, which operate according to the CAL rules. As a next step the implementation of the basic gates in the target technology is investigated. The limitations with respect to delay insensitivity are pinpointed and appropriate design constraints are derived.
The impacts of the findings are used to improve the design flow.
Furthermore, the results have allowed us designing our asynchronous processor ASPEAR. The development of an improved pipeline concept, the application of pre-compiled basic gates using Quartus, and the new library providing these gates to the synthesis tools are verified with the successful implementation of the processor.