This work presents the design and implementation of a fully integrated receiver in 0.13m CMOS for the 17.2GHz WLAN/ISM band. The main challenges are the high frequency of operation, high integration level and low power consumption. This thesis explores possible solutions for these challenges by careful active and passive component design, circuit design and receiver partitioning to achieve an optimum result. A completely integrated receiver has been designed using the 0.13m CMOS technology from Infineon Technologies AG. By avoiding the mandatory external filters of classical heterodyne receivers, a so-called "sliding-IF" double-conversion architecture offers more flexibility for the integration of a complete receiver on a single chip. As introduction, several receiver architectures are presented and propagation effects are discussed. A general design flow, starting with receiver specifications and processing up to building blocks is documented. Understanding the behaviour of a MOS transistor is important for high frequency circuit design. Integrated passive components are even more crucial to the performance of the building blocks and are described in depth.
Design and measurement results of single building blocks, such as low noise amplifiers (LNA), mixers, dividers and voltage-controlled oscillators (VCO), demonstrate the functionality. The fabricated testchip advances the state-of-the-art of receiver design by using a chip area of only 1.2mm and a power consumption of 180mA from a 1.5V supply . It includes a low-noise amplifier, a first down-conversion mixer, an IF-amplifier, I/Q-mixers, a fully integrated VCO, a 4:1 I/Q-divider and baseband amplifiers to drive the 50 Ohm I/Q-outputs.